1. Field of the Invention
The present invention relates to a logic circuit, particularly to a stack structure FETs logic circuit composed of field effect transistors that operates preferably at a voltage of 1 V or more and in ultra-high speed operation.
2. Description of the Related Art
The speed of electrons in a GaAs semiconductor is faster than that in a Si semiconductor by several times. Further, since a semi-insulating substrate can be easily manufactured, the parasitic capacitance of the circuit to be integrated can be reduced. With GaAs semiconductor devices, logic operations can be performed at a high speed. Thus, GaAs semiconductor devices have been intensively researched and developed in many laboratories in the world.
Among various basic circuit models of GaAs semiconductor devices, it is said that a direct coupled FET logic (hereinafter referred to as DCFL circuit) with an enhancement type field effect transistor (hereinafter referred to as FET) is simple structure and suitable for integration. In addition, the DCFL circuit does not require a high power supply voltage. With the DCFL circuit as a basic circuit, a gate array with an integration of 100 K gates has been commercially available.
As shown in FIG. 7, in the GaAs DCFL circuit, a drain electrode of a depletion type FET 51 used as a load is connected to a power supply terminal 100. A gate electrode and a source electrode of the depletion type FET 51 are connected to an output terminal 12. A drain electrode of an enhancement type FET 52 is connected to the output terminal 12. A gate electrode of the enhancement type FET 52 is connected to an input terminal 11. A source electrode of the enhancement type FET 52 is connected to a power supply terminal 101. The FETs 51 and 52 as inverters are followed by FETs 53 and 54 as inverters. Output signals of the FETs 53 and 54 are supplied from an output terminal 17.
When a voltage that is satisfactorily higher than the voltage of the source electrode of the FET 52 is supplied to the input terminal 11, a current flows in the enhancement type FET 52. Thus, the voltage at the output terminal 12 decreases. On the other hand, when a low voltage is supplied to the input terminal 11, no current flows in the enhancement type FET 52. Thus, the voltage at the output terminal 12 is maintained at a high voltage. Further, when the voltage at the output terminal 12 is a low voltage, the voltage at the output terminal 17 is a high level. In addition, when the voltage at the output terminal 12 is a high voltage, the voltage at the output terminal 17 is a low level.
Since the DCFL circuit shown in FIG. 7 is used along with an Si bipolar ECL (Emitter Coupled FET Logic) circuit, as a power supply voltage between the power supply terminal 100 and the power supply terminal 101, a negative power supply at -5.2 V, -4.5 V, -3.3 V, or -2.0 V is used.
On the other hand, the DCFL circuit composed of a compound semiconductor can operate at a high speed with a power supply voltage that is much lower than the above-described power supply voltage. In addition, when the DCFL circuit is operated at a power supply voltage that is higher than a gate forward turn-on voltage, a current flows from a gate Schottky electrode of the FET 54 of the next stage. This current does not contribute to driving the load, but a loss power of the circuit.
As a simplest and most effective means for decreasing the power consumption of the DCFL circuit, the power supply voltage is decreased. By setting the power supply voltage to the level lower than the Schottky barrier height of the FET, the current loss can be reduced. However, in this case, since a dedicated power supply for the GaAs DCFL circuit should be newly disposed in the system, this means is not practical.
As related art references that solve such a problem of the DCFL circuit and allow the power consumption to be reduced, for example Japanese Patent Laid-Open Publication Nos. 3-19422 and 6-104734 have been disclosed. In these related art references, logic circuits of which DCFL circuits are disposed in a plurality of stacking stages have been proposed.
In the conventional vertical stacking DCFL circuit shown in FIG. 5, a virtual voltage (virtual power supply terminal) 110 that is not connected to the outside is disposed between a power supply terminal 100 and a power supply terminal 101. The power supply terminal 100 is connected to the outside of the circuit. The voltage at the power supply terminal 100 is higher than the voltage at the power supply terminal 101. By operating a DCFL circuit between the power supply terminal 100 and the virtual power supply portion 110 or a DCFL circuit between the virtual power supply portion 110 and the power supply terminal 101, a current loss is re-used. Thus, the power consumption is reduced. As the DCFL circuit, FETs 53 and 54 as inverter circuits are used as a load of the output terminal 12. FETs 55 and 56 are used as a load of a level-shifting circuit.
In the circuit shown in FIG. 5, when a signal of a logic circuit that operates between the power supply terminal 100 and the virtual voltage portion 110 (this logic circuit is referred to as high voltage logic portion) is input to a logic circuit that operates between the virtual voltage portion 110 and the power supply terminal 101 (this logic circuit is referred to as low voltage logic portion), a level shifting circuit 21 shown in FIG. 5 is required.
Referring to FIG. 5, the level shifting circuit 21 is composed of for example an enhancement type FET 64, a diode 71, and a depletion type FET 65. In this circuit, the voltage of the input signal is lowered for the forward turn-on voltage of the diode 71.
In addition, to stabilize the virtual voltage portion 110, each of the voltage between the power supply terminal 100 and the virtual voltage portion 110 and the voltage between the virtual voltage portion 110 and the power supply terminal 101 is set to a higher voltage than the gate Schottky forward turn-on voltage of the FET. Thus, when a signal is connected from the high voltage logic portion to the low voltage logic portion, at least one diode is required. Consequently, the level shifting circuit 21 should be structured so that it operates between the power supply terminal 100 and the power supply terminal 101.
Since a current always flows in the level shifting circuit under a high voltage condition, the power consumption is large. Consequently, as the number of connections from the high voltage logic portion to the low voltage logic portion increases, the power consumption increases.
This applied to signal connections from the low voltage logic portion to the high voltage logic portion. As shown in FIG. 6, a level shifting circuit 22 composed of an enhancement type FET 64, a diode 71, and a depletion type FET 65 is required. In FIG. 6, FETs 58 and 67 as inverters are used for a level-shifted load. FETs 53 and 54 as inverters are used for a load of an output terminal 12.
The level shifting circuit 22 is structured by connecting at least one diode between a load DFET circuit and a drive FET so as to prevent the output voltage of the DCFL circuit from increasing to the voltage between the power supply terminal 100 and the power supply terminal 101. The output voltage swing of the output terminal 58 is decreased for the forward turn-on voltage of the diode 71.
However, since this circuit requires a high voltage, as the number of signal connections between the high voltage logic portion and the low voltage logic portion increases, the power consumption cannot be decreased.